Integration of amorphorous silicon transmit and receive structures with GaAs or InP processed devices

ABSTRACT

A device and a process for integrating light energy transmit and/or receive functions with active devices such as GaAs or InP devices or light emitting devices, such as lasers. The device and process includes forming a passivation layer on top of the active device and forming a silicon photodetector on top of the passivation layer. The photodetector may be formed utilizing a standard solar cell growth process and may be formed as a mesa on top of the active or light-emitting device, thus forming a relatively less complicated semiconductor with an integrated monitoring device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a process for semiconductordevices and more particularly to a process for integrating light energytransmit and/or receive functions with existing semiconductor devices,such as GaAs or InP devices.

[0003] 2. Description of the Prior Art

[0004] Various semiconductors are known, such as high-electron mobilitytransistor (HEMT) and heterojunction bipolar transistor (HBT) activedevices as well as light-emitting devices, such as laser diodes, inwhich it is necessary to monitor performance of the device duringoperation. For example, for light-emitting devices, such as lasers,performance is normally monitored by way of a photodetector. Thephotodetector is used to monitor the intensity of the light indicatingdevice. Such photodetectors are known to be fabricated separately andepoxied directly to the light-emitting device. However, such a processis relatively inefficient since it requires separate processing of thephotodetector and also requires attaching of the photodetector to thesemiconductor device. Such an inefficient process thus increases thecost of devices which require monitoring.

[0005] As such, processes have been developed for integratingphotodetectors into a light emitting device, such as a laser, forexample, as disclosed in U.S. Pat. Nos. 5,757,837 and 6,023,485.However, the integration of the photodetectors into the light-emittingdevices as disclosed in these patents involves relatively complicatedprocesses and only provides limited performance. For example, U.S. Pat.No. 5,757,834 discloses a vertical cavity surface emitting laser with anintegrally formed photodetector. The photodetector is formed as anintracavity quantum well photodetector, disposed at the opticalintensity peak at the Fabry-Perot wavelength. In particular, the laseris formed on a GaN substrate and includes an n-doped distributed Braggreflector (DBR) mirror stack. An active gain region is formed on top ofthe n-doped DBR mirror stack and includes a one wavelength spacer and aquantum well stack. A p-doped DBR mirror stack is formed on top of theactive gain region. The intracavity quantum well photodetector is formedon top of the p-doped DBR mirror stack and includes a 5λ/4 spacer withan In_(0.2) Ga_(0.8)As quantum well. On top of the photodetector anothern-doped DBR mirror stack is formed.

[0006] The laser emits light from the underside of the GaAn substrate.Reflected light is sensed by the photodetector to provide an indicationof the intensity of the laser light. Although the system disclosed inthe '837 patent discloses an integrally-formed photodetector, theprocessing steps are rather complicated and include the formation of aquantum well sandwiched between two DBRs.

[0007] U.S. Pat. No. 6,023,485 also discloses a vertical cavity surfaceemitting laser diode with an integrated PIN photo diode. In thisembodiment, the PIN diode is formed on top of a vertical cavity surfaceemitting laser. The PIN diode is formed as a lower stack of n-dopedDBRs, which are shared with the laser. An intrinsic region and p-dopedupper stack of DBRs are formed on top of the PIN diode. Ion implantationis used to damage a portion of the upper stack of DBRs in order todefine high resistivity damaged areas to confine the light paths in theregion of the upper stack of DBRs. As such, the device is relativelycomplicated to fabricate. Thus, there is a need for a monitoring devicethat can be integrated with various active devices that is relativelysimpler to fabricate than known devices.

SUMMARY OF THE INVENTION

[0008] Briefly, the present invention relates to a process forintegrating light energy transmit and/or receive functions with activedevices, such as GaAs, GaN or InP, and related devices, or lightemitting devices, such as lasers. Briefly, the process includes forminga monitoring device, such as a passivation layer on top of the active orlight emitting device and forming a silicon (crystalline or amorphous)photodetector or photodiode on top of the passivation layer. Thephotodetector/photodiode may be formed utilizing a standard solar cellgrowth process and may be formed as a mesa on top of the active orlight-emitting device, thus forming a relatively less complicatedintegrated photodetector/photodiode than known devices.

DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a cross-sectional elevational view of an exemplaryvertical cavity surface emitting diode laser.

[0010]FIG. 2 illustrates the formation of a passivation layer on top ofthe device illustrated in FIG. 1.

[0011]FIG. 3 illustrates the formation of an exemplary siliconphotodetector on top of the passivation layer illustrated in FIG. 2.

[0012]FIG. 4 is a cross-sectional elevational view of a vertical cavitysurface emitting diode laser with an integrally formed photodetector inaccordance with the present invention.

[0013]FIG. 5 is a plan view of the device illustrated in FIG. 4.

[0014]FIG. 6 is similar to FIG. 4 illustrating the operation of thephotodetector in accordance with the present invention.

DETAILED DESCRIPTION

[0015] The present invention relates to a relatively uncomplicatedprocess for forming one or more monitoring device, such as amorphoroussilicon transmit and receive structures on top of active devices, suchGaAs, GaN, and InP or related devices, as well as light-emittingdevices, such as lasers. An important aspect of the invention is thatthe light transmit and receive functions can be implemented by way of arelatively simple low-temperature, of amorphous silicon compositiondeposition process.

[0016] In accordance with the present invention, the light energytransmit and receive functions can be integrated on top of activedevices, such as GaAs, GaN and InP active, devices, for example, asdisclosed in commonly-owned U.S. Pat. Nos. 5,838,031; 5,710,523;5,550,520; 5,398,004; 5,389,896 and 5,355,096. In particular, the lightenergy transmit function may be integrally incorporated into a GaAs, GaNor InP active device, such as an amplifier, which would allow visualinspection of the operation of the amplifier connected to the lightemitting diode. On the other hand, the light energy receive function maybe used to detect light, for example, from light-emitting devices, suchas lasers and laser diodes, for example as disclosed in commonly-ownedU.S. Pat. No. 5,038,356, to monitor the light intensity of thelight-emitting device to provide an indication of the performancelight-emitting device.

[0017] The present invention is shown and illustrated as beingintegrated on top of a semiconductor laser diode and more particularlyto a vertical cavity surface emitting diode laser (VCSEL), as describedin detail in commonly-owned U.S. Pat. No. 5,038,356, hereby incorporatedby reference. It is to be understood, however, that the integrationprocess in accordance with the present invention may be utilized withvirtually any GaAs or InP active devices, as well as various types oflight-emitting devices, to provide additional functionality on a singleGaAs, or InP substrate.

[0018] Turning to FIG. 1, the silicon process for forming a lighttransmitting or light receiving device is shown being formed on top of avertical cavity surface emitting diode laser described in detail incommonly-owned U.S. Pat. No. 5,038,356, hereby incorporated byreference. Briefly, the VCSEL, generally identified with the referencenumeral 20, may be formed by a two-step metal organic chemical vapordeposition (MOCVD) crystal growth process or by molecular beam epitaxy(MBE). As shown, the VCSEL includes a substrate 22, for example, ap-doped InP, GaAs or other substrate. A p-doped semiconductor reflectoror distributed Bragg reflector (DBR) 24 is formed on top of thesubstrate 22. A p-cladding layer 26 is next formed on top of thesemiconductor reflector layer 24. The p-cladding layer may be formed ofAl_(x)As_(1-x). An active layer, formed, for example, from multiplequantum wells, may be disposed between the p-cladding layer 26 and ann-cladding layer 30. A back reflector layer 32 may be formed on top ofthe n-cladding layer 30.

[0019] The front reflector 24 may be distributive Bragg reflector formedfrom 5 to 10 high/low index pairs for example, or a certain number ofpair depending on the light wavelength. The back reflector 32 may beformed from 70 to 100 high/low index pairs for example, or a certainnumber of pair depending on the light wavelength.

[0020] Unlike the VCSEL disclosed in commonly-owned U.S. Pat. No.5,038,356, the back reflector layer 32 is not formed as a mesa. Ratherthe back reflector layer 32 is allowed to extend across the surface ofthe entire device, as generally shown in FIG. 1. The balance of thedetails for forming the vertical cavity surface emitting diode laser areas generally disclosed in commonly-owned U.S. Pat. No. 5,038,356.

[0021] In accordance with an important aspect of the invention, arelatively low temperature, i.e. 250° C.-550° C., silicon dioxide orsilicon nitride passivation layer 34 is formed on top of the VCSEL 20 bylow pressure chemical vapor deposition (LPCVD). A window 36 (FIG. 2) isetched through passivation layer 34 to enable the photodetector todetect reflected light, as will be discussed in more detail below. Thewindow 36 may be formed by masking the window 36 by standardphotolithographic techniques and dry etching to remove that portion ofthe passivation layer 34 to form the window 36. The dry etching may befollowed up by a wet etch process to clean passivation material residuefrom the upper reflector layer 32.

[0022] After the window 36 is formed in the passivation layer 34, thephotodetector is formed thereupon. The photodetector may be implementedas a standard solar cell growth process. In particular, referring toFIG. 3, a p-type conductive transparency oxide 38 (CTO) formed from, forexample, ZnO having a thickness of, for example, 150 nm is formed on topof the passivation layer 34 and window 36. Another silicon dioxide layer40 may be formed on top of the CTO layer 38. The silicon dioxide layer40 may be formed with a thickness of thousand angstroms. A second CTOlayer (SnO) Tin Oxide with fluor doped 42 is formed on top of thesilicon dioxide layer 40 from ZnO having a thickness of 150 nm.

[0023] A p-doped amorphorous silicon material composition layer 44 isformed on top of the second CTO layer 42. The p-doped amorphoroussilicon material composition may be formed with a thickness of 10-20 nm.An un-doped amorphorous silicon absorbent layer 46 is sandwiched betweenthe p-doped amorphorous silicon material composition layer 44 and ann-doped amorphorous silicon composition layer 48. The un-dopedamorphorous silicon absorbent layer 46 may be formed with a thicknessbetween 200 nm-300 nm. The n-doped amorphorous silicon composition layer48 may be formed with a thickness of 100 nm-150 nm. Finally, a third CTOlayer 50 may be formed on top of the n-doped amorphorous siliconcomposition layer 48. The third CTO layer 50 is formed from ZnO having athickness of, for example, 150 nm.

[0024] Turning to FIG. 4, the next processing level relates todepositing an n-contact metal 52 for the photodetector contact on top ofthe third CTO layer 50. The n-contact metal 52 is deposited and liftedoff by standard photolithography and metal deposition techniques to forman n-contact for the photodetector. After the n contact 52 is formed,the photodetector is formed as a mesa using standard semiconductorprocessing techniques, for example, and etching through layer 42 up tolayer 40. After the mesa 54 is formed, a photodetector p-type contact 58is formed by conventional semiconductor processing techniques to formthe metallization pattern 58. Subsequently, a p-metal is deposited andlifted off to form the metallization pattern 60 for the photodetectorp-contact. Subsequently, an n-VCSEL metallization pattern 62 is formed.The metallization pattern 62 is formed by etching through the layer 34and depositing and lifting of an n-type metal TiPtAu by conventionaltechniques, forming an integrated device.

[0025] The device may then be mounted upside down to a carrier 64, forexample, as disclosed in U.S. Pat. No. 5,038,356. Subsequently, thesubstrate layer 22 may be lapped and polished to the desired thickness,for example, 75-100 microns. A window 66 may be formed in the bottom ofthe substrate 22 by standard photolithography and etching techniques.After the window 66 is formed, a p-type VCSEL contact (not shown) may beformed within the window to contact the layer 24 by standard lithographytechniques.

[0026] An exemplar integrated device is illustrated in FIG. 6 andidentified with the reference numeral 70. As indicated in U.S. Pat. No.5,038,356, the laser emits light in a direction generally perpendicularto the planar layers of the device out the window 66, as generallyindicated by the arrow 72. The photodetector, generally identified withthe reference numeral 74, receives leakage light back through the topreflective stack 32 and window 36, which, in turn, is absorbed into thedetector 74 to provide an indication of the operation of the VCSELintegrally formed therewith.

[0027] Obviously, many modifications and variations of the presentinvention are possible in light of the above teachings. For example,various known photodetectors and photodiodes may be formed on top of theactive or light emitting device to provide an integrated device withadditional functionality in accordance with present invention. Thus, itis to be understood that, within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedabove.

What is claimed is:
 1. A semiconductor with integrated monitoringcomprising: a first semiconductor formed on a predetermined substrate; apassivation layer formed on top of said first semiconductor device; anda monitoring device formed on top of said passivation layer.
 2. Thesemiconductor as recited in claim 1, wherein said first semiconductordevice is an active device.
 3. A semiconductor with integratedmonitoring comprising: a first semiconductor formed on a GaAs substrate;a passivation layer formed on top of said first semiconductor device;and a monitoring device formed on top of said passivation layer.
 4. Asemiconductor with integrated monitoring comprising: a firstsemiconductor formed on a InP substrate; a passivation layer formed ontop of said first semiconductor device; and a monitoring device formedon top of said passivation layer
 5. A semiconductor with integratedmonitoring comprising: a first semiconductor formed on a GaN substrate;a passivation layer formed on top of said first semiconductor device;and a monitoring device formed on top of said passivation layer
 6. Thesemiconductor as recited in claim 2, wherein said active device is anamplifier.
 7. The semiconductor as recited in claim 1, wherein saidfirst semiconductor device is a light emitting device.
 8. Thesemiconductor as recited in claim 6, wherein said light emitting deviceis a laser.
 9. The semiconductor as recited in claim 8, wherein saidlaser is a vertical cavity surface emitting laser (VCSEL).
 10. Thesemiconductor as recited in claim 1, wherein said monitoring device is alight transmitting device.
 11. The semiconductor as recited in claim 1,wherein said monitoring device is a light receiving device.
 12. Thesemiconductor as recited in claim 10, wherein said light transmittingdevice is a photodiode.
 13. The semiconductor as recited in claim 11,wherein said light receiving device is a photodetector.
 14. A processfor forming a semiconductor device with integrated monitoring comprisingthe steps of: a) forming a first semiconductor device on a substrate; b)forming a passivation layer on top of said first semiconductor device;and c) forming a monitoring device on top of said passivation layer. 15.A process for forming a semiconductor device with integrated monitoringcomprising the steps of: a) forming a first active semiconductor deviceon a substrate; b) forming a passivation layer on top of said firstsemiconductor device; and c) forming a monitoring device on top of saidpassivation layer.
 16. A process for forming a semiconductor device withintegrated monitoring comprising the steps of: a) forming a first activesemiconductor device on a GaAs substrate; b) forming a passivation layeron top of said first semiconductor device; and c) forming a monitoringdevice on top of said passivation layer.
 17. A process for forming asemiconductor device with integrated monitoring comprising the steps of:a) forming a first active semiconductor device on a InP substrate; b)forming a passivation layer on top of said first semiconductor device;and c) forming a monitoring device on top of said passivation layer. 18.A process for forming a semiconductor device with integrated monitoringcomprising the steps of: a) forming a first active semiconductor deviceon a GaN substrate; b) forming a passivation layer on top of said firstsemiconductor device; and c) forming a monitoring device on top of saidpassivation layer.
 19. The process as recited in claim 14, wherein step(a) includes forming a light emitting device on said substrate.
 20. Theprocess as recited in claim 14, wherein step (c) includes forming alight transmitting device on said passivation layer.
 21. The process asrecited in claim 14, wherein step (c) includes forming a light receivingdevice on said passivation layer.
 22. A process for forming asemiconductor device with integrated monitoring comprising the steps of:a) forming a first semiconductor device on a substrate; b) forming apassivation layer on top of said first semiconductor device; and c)forming a light receiving device on top of said passivation layer usinga low pressure chemical vapor deposition process to deposit an amorphoussilicon composition.